The present invention relates to a voltage regulator, and is suitable for application to a voltage regulator that is provided in a portable device such as a portable telephone or a PDA (Personal Digital Assistant), for example, and which has a protection function for preventing an output current from becoming an overcurrent (this function will hereinafter be referred to as an overcurrent protection function).
As shown in FIG. 16, in a typical voltage regulator 1 having an overcurrent protection function, a first input terminal N11 of a differential amplifier A1 is connected to a reference voltage source BGR1, and an output terminal O11 of the differential amplifier A1 is connected to the gate of a voltage and current controlling transistor Q1. The voltage and current controlling transistor Q1 has a source connected to an input terminal Tin1 for a power supply voltage Vin supplied from an input voltage source, and has a drain connected to an output terminal Tout1 of the voltage regulator 1. An output capacitor C1, a load L1, and a voltage divider Z1 for dividing an output voltage Vout1 occurring at the output terminal Tout1 are connected in parallel with each other between the output terminal Tout1 and a ground GND. The voltage divider Z1 is formed by a first resistance Z11 and a second resistance Z12 (the first resistance and the second resistance will hereinafter be referred to as a first voltage dividing resistance and a second voltage dividing resistance) connected between the output terminal Tout1 and the ground GND. An intermediate connection point between the first voltage dividing resistance Z11 and the second voltage dividing resistance Z12 of the voltage divider Z1 is connected as a voltage dividing point P1 of division of the output voltage Vout1 to a second input terminal N12 of the differential amplifier A1.
The reference voltage source BGR1 generates a reference voltage Vref1 serving as a reference for generating the output voltage Vout1. The reference voltage source BGR1 supplies the reference voltage Vref1 to the first input terminal N11 of the differential amplifier A1. The voltage divider Z1 divides the output voltage Vout1 occurring at the output terminal Tout1 with a voltage dividing ratio selected by the resistance values of the first voltage dividing resistance Z11 and the second voltage dividing resistance Z12 at the voltage dividing point P1 to obtain a voltage for feedback to the differential amplifier A1. The voltage divider Z1 then supplies a divided voltage Vz1 obtained by thus dividing the output voltage Vout1 to the second input terminal N12 of the differential amplifier A1.
The differential amplifier A1 amplifies a difference voltage between the reference voltage Vref1 and the divided voltage Vz1, and supplies the amplified difference voltage as a control signal for generating the output voltage to the gate of the voltage and current controlling transistor Q1. The differential amplifier A1 increases or decreases the on resistance of the voltage and current controlling transistor Q1 by the control signal, and thus controls the on resistance of the voltage and current controlling transistor Q1. According to the control of the on resistance by the control signal, the voltage and current controlling transistor Q1 controls the current value of an output current Iout1 flowing between the drain and the source. The voltage regulator 1 charges the output capacitor C1 with the output current Iout1 flowing through the voltage and current controlling transistor Q1, thus generates the output voltage Vout1 at the output terminal Tout1, and supplies the output voltage Vout1 to the load L1.
Thus, when the output voltage Vout1 is varied due to a variation in the load L1, the voltage regulator 1 feeds back the varied output voltage Vout1 as the divided voltage Vz1 to the differential amplifier A1. On the basis of the difference voltage between the reference voltage Vref1 and the divided voltage Vz1, the differential amplifier A1 controls the on resistance of the voltage and current controlling transistor Q1 such that the divided voltage Vz1 obtained by dividing the output voltage Vout1 with the voltage dividing ratio selected by the resistance values R1 and R2 of the first voltage dividing resistance Z11 and the second voltage dividing resistance Z12 becomes substantially equal to the reference voltage Vref1, as expressed by Equation (1).
                              [                      Equation            ⁢                                                  ⁢            1                    ]                ⁢                                                                (          1          )                ⁢                                                          Vout        =                  Vref          ×                      [                                          R1                +                R2                            R2                        ]                                                          
The voltage regulator 1 can thus generate the output voltage Vout1 having a predetermined constant voltage value at the output terminal Tout1. Incidentally, Vout in Equation (1) denotes the voltage value of the output voltage Vout1. Vref denotes the voltage value of the reference voltage Vref1.
Incidentally, letting Iout be the current value of the output current Iout1 flowing to the output terminal Tout1 when the output voltage Vout1 is generated in the voltage regulator 1, a power loss Pout at the voltage and current controlling transistor Q1 at this time can be obtained by multiplying a result of subtraction of the output voltage Vout1 from the power supply voltage Vin by the output current Iout1, as expressed by Equation (2).[Equation 2]  (2)Pout=(Vin−Vout)×Iout
The voltage regulator 1 has an overcurrent protection circuit unit 2 connected to an intermediate connection point between the output terminal O11 of the differential amplifier A1 and the gate of the voltage and current controlling transistor Q1. At a time of operation of the voltage regulator 1, the overcurrent protection circuit unit 2 adjusts the value of the control signal supplied from the differential amplifier A1 to the gate of the voltage and current controlling transistor Q1. When the load L1 is short-circuited or becomes an overload, for example, the overcurrent protection circuit unit 2 forcefully prevents the current value Iout of the output current Iout1 from exceeding a first current value as an upper limit value selected in advance (this current value will hereinafter be referred to as an upper limit value). Therefore, the overcurrent protection circuit unit 2 prevents the output current Iout1 from flowing as an overcurrent to the load L1, and thus protects the load L1 side from heat generation or the like due to the overcurrent.
In this case, the voltage regulator 1 implements the overcurrent protection function by limiting the current value Iout of the output current Iout1 to the upper limit value or lower according to a current limiting characteristic represented with an axis of ordinates denoting the output voltage Vout1 and an axis of abscissas denoting the output current Iout1. There are three kinds of current limiting characteristics as follows. As shown in FIG. 17, a first current limiting characteristic is a drooping characteristic in which after the current value Iout of the output current Iout1 reaches the upper limit value Imax, the current value Iout of the output current Iout1 (that is, the upper limit value Imax) is held constant (this drooping characteristic will hereinafter be referred to as a constant current type drooping characteristic).
As shown in FIG. 18, another current limiting characteristic is a drooping characteristic in which after the current value Iout of the output current Iout1 reaches the upper limit value Imax, the current value Iout of the output current Iout1 (that is, the upper limit value Imax) is lowered substantially linearly to a second current value Imin1 selected in advance as a lower limit value which current value is lower than the upper limit value Imax (this second current value will hereinafter be referred to as a lower limit value) so as to describe the shape of a chevron (this drooping characteristic will hereinafter be referred to as a chevron type drooping characteristic). As shown in FIG. 19, another current limiting characteristic is a drooping characteristic in which after the current value Iout of the output current Iout1 reaches the upper limit value Imax, the current value Iout of the output current Iout1 (that is, the upper limit value Imax) is lowered exponentially to a lower limit value Imin2 selected in advance (this drooping characteristic will hereinafter be referred to as a foldback type drooping characteristic).
Thus, in operation, the conventional, typical voltage regulator 1 limits the current value Iout of the output current Iout1 to the upper limit value Imax or lower by the overcurrent protection circuit unit 2 according to one of the constant current type drooping characteristic, the chevron type drooping characteristic, and the foldback type drooping characteristic as the current limiting characteristic. When such an overcurrent protection circuit unit 2 is provided in the voltage regulator 1, however, the voltage regulator 1 adjusts the value of the control signal supplied to the voltage and current controlling transistor Q1 according to the current limiting characteristic, and limits the current value Iout of the output current Iout1 to a low value even at a time of rising of the output voltage Vout1. The voltage regulator 1 therefore takes time to charge the output capacitor C1 at the time of rising of the output voltage Vout1. Consequently, as compared with a case where the overcurrent protection circuit unit 2 is not provided, it takes a longer time for the output current Iout1 to rise to a constant voltage value.
Accordingly, there is conventionally a voltage regulator 5 formed as shown in FIG. 20. The voltage regulator 5 controls the operation of an output transistor Q2 by an operational amplifier 6 on the basis of a reference voltage Vref2 supplied from a reference voltage generating circuit 7 to the operational amplifier 6 and a divided voltage Vz2 supplied from a voltage divider circuit 8 to the operational amplifier 6 which divided voltage is obtained by dividing an output voltage Vout2. The voltage regulator 5 generates the output voltage Vout2 from a power supply voltage VDD supplied via a power supply terminal 9 by the output transistor Q2, and outputs the generated output voltage Vout2 via an output terminal 10.
In this case, the voltage regulator 5 has a current limiting circuit 11 connected to the gate of the output transistor Q2 via a current limitation control circuit 12. The operational amplifier 6 in the voltage regulator 5 is activated in response to a chip enable signal S1 externally input to the operational amplifier 6 via a CE input terminal 13. In the voltage regulator 5, the chip enable signal S1 is also input to the current limitation control circuit 12 so that the current limitation control circuit 12 disconnects the gate of the output transistor Q2 from the current limiting circuit 11 for a predetermined period of time. When the predetermined period of time thereafter passes, the voltage regulator 5 connects the gate of the output transistor Q2 and the current limiting circuit 11 to each other to limit the current value of an output current according to the constant current type drooping characteristic by the current limiting circuit 11.
Thus, the conventional voltage regulator 5 speeds the rising of the output voltage Vout2 by not limiting the output current for the predetermined period of time when the output voltage Vout2 rises to a constant voltage value in response to the input of the chip enable signal S1 (for example see Japanese Patent Laid-Open No. 2002-91579 (page 4 and page 5, FIG. 1)).
As shown in FIG. 21, when power to a conventional direct-current power supply device 15 is turned on via a switch 16, a switching circuit 17 connects a reference voltage source 18 forming an overcurrent protection circuit with the constant current type drooping characteristic to an error amplifier 19, and thereby a reference voltage is supplied to the error amplifier 19. A control circuit 20 in the direct-current power supply device 15 operates on the basis of an output of the error amplifier 19 at this time to raise an output voltage detected at an output voltage detecting terminal Vs with the constant current type drooping characteristic.
After the output voltage stabilizes, the switching circuit 17 in the direct-current power supply device 15 connects the error amplifier 19 with an intermediate connection point P2 between voltage dividing resistances Z21 and Z22 forming an overcurrent protection circuit with the chevron type drooping characteristic in place of the reference voltage source 18. The direct-current power supply device 15 supplies the error amplifier 19 with a divided voltage obtained by dividing the output voltage by the voltage dividing resistances Z21 and Z22. When a load L2 is in an overcurrent state, and a voltage drop of a current detecting resistance Z23 is greater than the divided voltage, the direct-current power supply device 15 inputs an overcurrent signal amplified by the error amplifier 19 to an overcurrent signal input terminal Is of the control circuit 20 to make the control circuit 20 operate. The direct-current power supply device 15 lowers the output voltage detected at the output voltage detecting terminal Vs in the control circuit 20, and the overcurrent protection circuit with the chevron type drooping characteristic works.
Thus, the direct-current power supply device 15 starts in a state in which the overcurrent protection circuit with the constant current type drooping characteristic is working at the time of turning on power, and after the output voltage stabilizes, the overcurrent protection circuit with the chevron type drooping characteristic works to prevent an output current from becoming an overcurrent (see Japanese Patent Laid-Open No. Sho 63-78208 (page 2 and page 3, FIG. 1)).